Area: Computing
My Opensource IP Cores

I2S to Parallel Interface

This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device (microcontroller, IP block).

It's coded as a generic VHDL entity, so developer can choose the proper signal width (8/16/24 bit)

Downloads of project files and other details are available the related project page on opencores.org